Design and Simulation of Radix-8 Booth Encoder Multiplier for Signed and Unsigned Numbers

The multiplication operation is present in many parts of a digital system or digital computer, most notably in signal processing, graphics and scientific computation. With advances in technology, various techniques have been proposed to design multipliers, which offer high speed, low power consumption and lesser area. Thus making them suitable for various high speeds, low power compact VLSI implementations. These three parameters i.e. power, area and speed are always traded off. This thesis work is devoted for the design and simulation of Radix-8 Booth Encoder multiplier for signed-unsigned numbers. The Radix-8 Booth Encoder circuit generates n/3 the partial products in parallel. By extending sign bit of the operands and generating an additional partial product the signed of unsigned Radix-8 Booth Encoder multiplier is obtained. The Carry Save Adder (CSA) tree and the final Carry Look ahead (CLA) adder used to speed up the multiplier operation. Since signed and unsigned multiplication operation is performed by the same multiplier unit the required hardware and the chip area reduces and this in turn reduces power dissipation and cost of a system. Verilog coding of multiplier for signed and unsigned numbers using Radix-4 booth encoder and Radix-8 booth encoder for 8X8 bit multiplication and their FPGA implementation by Xilinx Synthesis Tool on Spartan 3 kit have been done. The output has been displayed on LED of Spartan 3 kit.